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authorFlorian Baumann <derflob@derflob.de>2021-02-13 17:42:23 +0100
committerFlorian Baumann <derflob@derflob.de>2021-02-13 17:42:23 +0100
commit2392463af8e7c7b34915ba1f85147e75a7e6cd76 (patch)
tree5618a79ec0fe89f9658f302eb9ff9c78d6342fa8
parent9b1635193fe51722b7bb292e0541c673480b2143 (diff)
downloadRJ45EEPROMKey-master.tar.gz
RJ45EEPROMKey-master.tar.bz2
use correct pinout for 25AA02E45-SNHEADmaster
-rw-r--r--RJ45EEPROMKey-cache.lib22
-rw-r--r--RJ45EEPROMKey.kicad_pcb605
-rw-r--r--RJ45EEPROMKey.sch222
3 files changed, 423 insertions, 426 deletions
diff --git a/RJ45EEPROMKey-cache.lib b/RJ45EEPROMKey-cache.lib
index e93bf8a..69c6206 100644
--- a/RJ45EEPROMKey-cache.lib
+++ b/RJ45EEPROMKey-cache.lib
@@ -19,24 +19,26 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
-# flobs-KiCad-lib_25AA02E48T
+# flobs-KiCad-lib_25AA02E48T-SN
#
-DEF flobs-KiCad-lib_25AA02E48T U 0 20 Y Y 1 F N
+DEF flobs-KiCad-lib_25AA02E48T-SN U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V C CNN
-F1 "flobs-KiCad-lib_25AA02E48T" 100 -250 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
+F1 "flobs-KiCad-lib_25AA02E48T-SN" 100 -250 50 H V L CNN
+F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOT23
$ENDFPLIST
DRAW
S -300 200 300 -200 1 1 10 f
-X SCK 1 400 100 100 L 50 50 1 1 I
-X GND 2 0 -300 100 U 50 50 1 1 W
-X MOSI 3 400 0 100 L 50 50 1 1 I
-X MISO 4 400 -100 100 L 50 50 1 1 T
-X ~CS 5 -400 -100 100 R 50 50 1 1 I
-X VDD 6 0 300 100 D 50 50 1 1 W
+X ~CS 1 -400 -100 100 R 50 50 1 1 I
+X MISO 2 400 -100 100 L 50 50 1 1 T
+X ~WP 3 -400 0 100 R 50 50 1 1 I
+X GND 4 0 -300 100 U 50 50 1 1 W
+X MOSI 5 400 0 100 L 50 50 1 1 I
+X SCK 6 400 100 100 L 50 50 1 1 I
+X ~HOLD 7 -400 100 100 R 50 50 1 1 I
+X VDD 8 0 300 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
diff --git a/RJ45EEPROMKey.kicad_pcb b/RJ45EEPROMKey.kicad_pcb
index 435c472..1e01a90 100644
--- a/RJ45EEPROMKey.kicad_pcb
+++ b/RJ45EEPROMKey.kicad_pcb
@@ -1,9 +1,9 @@
-(kicad_pcb (version 20171130) (host pcbnew 5.1.8)
+(kicad_pcb (version 20171130) (host pcbnew 5.1.9)
(general
(thickness 1.6)
(drawings 5)
- (tracks 49)
+ (tracks 56)
(zones 0)
(modules 7)
(nets 9)
@@ -12,8 +12,8 @@
(page A4)
(title_block
(title RJ45EEPROMKey)
- (date 2021-01-03)
- (rev v2)
+ (date 2021-02-13)
+ (rev v3)
(company Flobs)
)
@@ -43,8 +43,8 @@
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
- (zone_clearance 0.3)
- (zone_45_only no)
+ (zone_clearance 0.25)
+ (zone_45_only yes)
(trace_min 0.2)
(via_size 0.8)
(via_drill 0.4)
@@ -62,8 +62,8 @@
(mod_edge_width 0.12)
(mod_text_size 1 1)
(mod_text_width 0.15)
- (pad_size 2 1)
- (pad_drill 0.5)
+ (pad_size 2.25 0.5)
+ (pad_drill 1.75)
(pad_to_mask_clearance 0.051)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
@@ -98,14 +98,14 @@
)
(net 0 "")
- (net 1 "Net-(J1-Pad3)")
- (net 2 "Net-(J1-Pad4)")
- (net 3 "Net-(J1-Pad5)")
- (net 4 "Net-(J1-Pad6)")
- (net 5 "Net-(J1-Pad2)")
- (net 6 "Net-(J1-Pad7)")
- (net 7 GND)
- (net 8 VCC)
+ (net 1 "Net-(J1-Pad2)")
+ (net 2 "Net-(J1-Pad7)")
+ (net 3 GND)
+ (net 4 VCC)
+ (net 5 /~CS)
+ (net 6 /MISO)
+ (net 7 /MOSI)
+ (net 8 /SCK)
(net_class Default "This is the default net class."
(clearance 0.2)
@@ -114,67 +114,64 @@
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
+ (add_net /MISO)
+ (add_net /MOSI)
+ (add_net /SCK)
+ (add_net /~CS)
(add_net GND)
(add_net "Net-(J1-Pad2)")
- (add_net "Net-(J1-Pad3)")
- (add_net "Net-(J1-Pad4)")
- (add_net "Net-(J1-Pad5)")
- (add_net "Net-(J1-Pad6)")
(add_net "Net-(J1-Pad7)")
(add_net VCC)
)
- (module Capacitor_SMD:C_0402_1005Metric (layer F.Cu) (tedit 5F68FEEE) (tstamp 5FF28375)
- (at 26.25 17.5 90)
- (descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+ (module Capacitor_SMD:C_0805_2012Metric (layer F.Cu) (tedit 5F68FEEE) (tstamp 5FF28375)
+ (at 28 17.5 270)
+ (descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags capacitor)
(path /5FF2388F)
(attr smd)
- (fp_text reference C1 (at 1.25 0 180) (layer F.SilkS)
+ (fp_text reference C1 (at 2.25 0 180) (layer F.SilkS)
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
- (fp_text value 100nF (at 0 1.16 90) (layer F.Fab)
+ (fp_text value 100nF (at 0 1.68 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
- (effects (font (size 0.25 0.25) (thickness 0.04)))
+ (effects (font (size 0.5 0.5) (thickness 0.08)))
)
- (fp_line (start -0.5 0.25) (end -0.5 -0.25) (layer F.Fab) (width 0.1))
- (fp_line (start -0.5 -0.25) (end 0.5 -0.25) (layer F.Fab) (width 0.1))
- (fp_line (start 0.5 -0.25) (end 0.5 0.25) (layer F.Fab) (width 0.1))
- (fp_line (start 0.5 0.25) (end -0.5 0.25) (layer F.Fab) (width 0.1))
- (fp_line (start -0.107836 -0.36) (end 0.107836 -0.36) (layer F.SilkS) (width 0.12))
- (fp_line (start -0.107836 0.36) (end 0.107836 0.36) (layer F.SilkS) (width 0.12))
- (fp_line (start -0.91 0.46) (end -0.91 -0.46) (layer F.CrtYd) (width 0.05))
- (fp_line (start -0.91 -0.46) (end 0.91 -0.46) (layer F.CrtYd) (width 0.05))
- (fp_line (start 0.91 -0.46) (end 0.91 0.46) (layer F.CrtYd) (width 0.05))
- (fp_line (start 0.91 0.46) (end -0.91 0.46) (layer F.CrtYd) (width 0.05))
- (pad 2 smd roundrect (at 0.48 0 90) (size 0.56 0.62) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 7 GND))
- (pad 1 smd roundrect (at -0.48 0 90) (size 0.56 0.62) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 8 VCC))
- (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0402_1005Metric.wrl
+ (fp_line (start -1 0.625) (end -1 -0.625) (layer F.Fab) (width 0.1))
+ (fp_line (start -1 -0.625) (end 1 -0.625) (layer F.Fab) (width 0.1))
+ (fp_line (start 1 -0.625) (end 1 0.625) (layer F.Fab) (width 0.1))
+ (fp_line (start 1 0.625) (end -1 0.625) (layer F.Fab) (width 0.1))
+ (fp_line (start -0.261252 -0.735) (end 0.261252 -0.735) (layer F.SilkS) (width 0.12))
+ (fp_line (start -0.261252 0.735) (end 0.261252 0.735) (layer F.SilkS) (width 0.12))
+ (fp_line (start -1.7 0.98) (end -1.7 -0.98) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.7 -0.98) (end 1.7 -0.98) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.7 -0.98) (end 1.7 0.98) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 1.7 0.98) (end -1.7 0.98) (layer F.CrtYd) (width 0.05))
+ (pad 2 smd roundrect (at 0.95 0 270) (size 1 1.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+ (net 3 GND))
+ (pad 1 smd roundrect (at -0.95 0 270) (size 1 1.45) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+ (net 4 VCC))
+ (model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
- (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 5E46FCD3)
- (at 21.75 17.5)
+ (module Package_SO:SOIC-8_3.9x4.9mm_P1.27mm (layer F.Cu) (tedit 5D9F72B1) (tstamp 6027E5DC)
+ (at 23.25 17.5)
(descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
(tags "SOIC SO")
(path /5E4700AB)
(attr smd)
- (fp_text reference U1 (at 0 -3.4) (layer F.SilkS)
- (effects (font (size 1 1) (thickness 0.15)))
+ (fp_text reference U1 (at 0 -3.25) (layer F.SilkS)
+ (effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 25AA02E48T (at 0 3.4) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
- (fp_text user %R (at 0 0) (layer F.Fab)
- (effects (font (size 0.98 0.98) (thickness 0.15)))
- )
(fp_line (start 0 2.56) (end 1.95 2.56) (layer F.SilkS) (width 0.12))
(fp_line (start 0 2.56) (end -1.95 2.56) (layer F.SilkS) (width 0.12))
(fp_line (start 0 -2.56) (end 1.95 -2.56) (layer F.SilkS) (width 0.12))
@@ -188,20 +185,25 @@
(fp_line (start -3.7 2.7) (end 3.7 2.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 2.7) (end 3.7 -2.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 -2.7) (end -3.7 -2.7) (layer F.CrtYd) (width 0.05))
- (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
- (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25))
+ (fp_text user %R (at 0 0) (layer F.Fab)
+ (effects (font (size 0.98 0.98) (thickness 0.15)))
+ )
+ (pad 8 smd roundrect (at 2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+ (net 4 VCC))
+ (pad 7 smd roundrect (at 2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
+ (net 4 VCC))
(pad 6 smd roundrect (at 2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 8 VCC))
+ (net 8 /SCK))
(pad 5 smd roundrect (at 2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 1 "Net-(J1-Pad3)"))
+ (net 7 /MOSI))
(pad 4 smd roundrect (at -2.475 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 2 "Net-(J1-Pad4)"))
+ (net 3 GND))
(pad 3 smd roundrect (at -2.475 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 3 "Net-(J1-Pad5)"))
+ (net 4 VCC))
(pad 2 smd roundrect (at -2.475 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 7 GND))
+ (net 6 /MISO))
(pad 1 smd roundrect (at -2.475 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
- (net 4 "Net-(J1-Pad6)"))
+ (net 5 /~CS))
(model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-8_3.9x4.9mm_P1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
@@ -209,339 +211,312 @@
)
)
- (module flobs-KiCad-footprints:RJ45Pads_sloted (layer F.Cu) (tedit 5FF2218D) (tstamp 5E46FEAD)
+ (module flobs-KiCad-footprints:RJ45Pads_sloted (layer F.Cu) (tedit 6027FDD5) (tstamp 5E46FEAD)
(at 16.25 17.5)
(path /5E471B81)
- (fp_text reference J1 (at 1 0 90) (layer F.SilkS)
- (effects (font (size 1 1) (thickness 0.15)))
+ (fp_text reference J1 (at 0.75 3.5 180) (layer F.SilkS)
+ (effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value RJ45Pads (at 0 -4.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole oval (at -1.125 3.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 7 GND))
+ (net 3 GND))
(pad 2 thru_hole oval (at -1.125 2.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 5 "Net-(J1-Pad2)"))
+ (net 1 "Net-(J1-Pad2)"))
(pad 3 thru_hole oval (at -1.125 1.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 1 "Net-(J1-Pad3)"))
+ (net 5 /~CS))
(pad 4 thru_hole oval (at -1.125 0.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 2 "Net-(J1-Pad4)"))
+ (net 6 /MISO))
(pad 5 thru_hole oval (at -1.125 -0.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 3 "Net-(J1-Pad5)"))
+ (net 7 /MOSI))
(pad 6 thru_hole oval (at -1.125 -1.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 4 "Net-(J1-Pad6)"))
+ (net 8 /SCK))
(pad 7 thru_hole oval (at -1.125 -2.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 6 "Net-(J1-Pad7)"))
+ (net 2 "Net-(J1-Pad7)"))
(pad 8 thru_hole oval (at -1.125 -3.5) (size 2.25 0.5) (drill oval 1.75 0.4) (layers *.Cu *.Mask)
- (net 8 VCC))
+ (net 4 VCC))
)
(module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 5E470857) (tstamp 5E470A62)
- (at 28.25 20.25)
+ (at 30.75 20.25)
(fp_text reference REF** (at 0 -2.54) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SolderWirePad_single_0-8mmDrill (at -15.25 -7.5) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
- (pad 1 thru_hole oval (at 0 0) (size 2 1) (drill 0.5) (layers *.Cu *.Mask))
+ (pad 1 thru_hole oval (at 0 0) (size 3 1) (drill 0.5) (layers *.Cu *.Mask))
)
(module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 5E470857) (tstamp 5E470A87)
- (at 28.25 18.5)
+ (at 30.75 18.5)
(fp_text reference REF** (at 0 -2.54) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SolderWirePad_single_0-8mmDrill (at 0 2.54) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
- (pad 1 thru_hole oval (at 0 0) (size 2 1) (drill 0.5) (layers *.Cu *.Mask))
+ (pad 1 thru_hole oval (at 0 0) (size 3 1) (drill 0.5) (layers *.Cu *.Mask))
)
(module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 5E470857) (tstamp 5E470A93)
- (at 28.25 16.5)
+ (at 30.75 16.5)
(fp_text reference REF** (at 0 -2.54) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SolderWirePad_single_0-8mmDrill (at 0 2.54) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
- (pad 1 thru_hole oval (at 0 0) (size 2 1) (drill 0.5) (layers *.Cu *.Mask))
+ (pad 1 thru_hole oval (at 0 0) (size 3 1) (drill 0.5) (layers *.Cu *.Mask))
)
- (module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 5E470857) (tstamp 5E470A7B)
- (at 28.25 14.75)
+ (module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 6027E382) (tstamp 5E470A7B)
+ (at 30.75 14.75)
(fp_text reference REF** (at 0 -2.54) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SolderWirePad_single_0-8mmDrill (at 0 2.54) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
- (pad 1 thru_hole oval (at 0 0) (size 2 1) (drill 0.5) (layers *.Cu *.Mask))
+ (pad 1 thru_hole oval (at 0 0) (size 3 1) (drill 0.5) (layers *.Cu *.Mask))
)
- (gr_text "Flob's\nEEPROM Key" (at 19.5 17.5 90) (layer B.SilkS)
+ (gr_text "Flobs\nRJ45 EEPROM\nKeyfob" (at 26.5 17.5 -90) (layer B.SilkS)
(effects (font (size 0.75 0.75) (thickness 0.1875)) (justify mirror))
)
- (gr_line (start 30.75 13) (end 13.25 13) (layer F.SilkS) (width 0.12) (tstamp 5E46FDD9))
- (gr_line (start 30.75 22) (end 30.75 13) (layer F.SilkS) (width 0.12))
- (gr_line (start 13.25 22) (end 30.75 22) (layer F.SilkS) (width 0.12))
- (gr_line (start 13.25 13) (end 13.25 22) (layer F.SilkS) (width 0.12))
+ (gr_line (start 33.25 13) (end 13.25 13) (layer Edge.Cuts) (width 0.12) (tstamp 5E46FDD9))
+ (gr_line (start 33.25 22) (end 33.25 13) (layer Edge.Cuts) (width 0.12))
+ (gr_line (start 13.25 22) (end 33.25 22) (layer Edge.Cuts) (width 0.12))
+ (gr_line (start 13.25 13) (end 13.25 22) (layer Edge.Cuts) (width 0.12))
- (via (at 17.237347 19.012653) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 1))
- (segment (start 17.224694 19) (end 17.237347 19.012653) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 15.125 19) (end 17.224694 19) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 17.237347 19.578338) (end 18.159009 20.5) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 17.237347 19.012653) (end 17.237347 19.578338) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 18.159009 20.5) (end 21.25 20.5) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 22.345 19.405) (end 24.225 19.405) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 21.25 20.5) (end 22.345 19.405) (width 0.25) (layer F.Cu) (net 1))
- (segment (start 17.224694 19) (end 17.237347 19.012653) (width 0.25) (layer B.Cu) (net 1))
- (segment (start 15.125 19) (end 17.224694 19) (width 0.25) (layer B.Cu) (net 1))
- (via (at 17.25 13.999996) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 8))
- (segment (start 15.125 14) (end 17.249996 14) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 17.249996 14) (end 17.25 13.999996) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 23.25 18.135) (end 24.225 18.135) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 22.25 15) (end 22.25 17.135) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 21.249996 13.999996) (end 22.25 15) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 22.25 17.135) (end 23.25 18.135) (width 0.25) (layer F.Cu) (net 8))
- (segment (start 17.25 13.999996) (end 21.249996 13.999996) (width 0.25) (layer F.Cu) (net 8))
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diff --git a/RJ45EEPROMKey.sch b/RJ45EEPROMKey.sch
index fdade3b..39f4b82 100644
--- a/RJ45EEPROMKey.sch
+++ b/RJ45EEPROMKey.sch
@@ -5,8 +5,8 @@ $Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title "RJ45EEPROMKey"
-Date "2021-01-03"
-Rev "v2"
+Date "2021-02-13"
+Rev "v3"
Comp "Flobs"
Comment1 ""
Comment2 ""
@@ -14,154 +14,174 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
-L flobs-KiCad-lib:25AA02E48T U1
+L flobs-KiCad-lib:25AA02E48T-SN U1
U 1 1 5E4700AB
-P 3900 2900
-F 0 "U1" H 4150 3150 50 0000 C CNN
-F 1 "25AA02E48T" H 3550 3150 50 0000 C CNN
-F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 3900 2900 50 0001 C CNN
-F 3 "" H 3900 2900 50 0001 C CNN
-F 4 "C150800" H 3900 2900 50 0001 C CNN "JLCPCB#"
- 1 3900 2900
+P 3000 1500
+F 0 "U1" H 3250 1750 50 0000 C CNN
+F 1 "25AA02E48T" H 2650 1750 50 0000 C CNN
+F 2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" H 3000 1500 50 0001 C CNN
+F 3 "" H 3000 1500 50 0001 C CNN
+F 4 "C150800" H 3000 1500 50 0001 C CNN "JLCPCB#"
+ 1 3000 1500
1 0 0 -1
$EndComp
$Comp
L flobs-KiCad-lib:RJ45Pads J1
U 1 1 5E471B81
-P 1850 2900
-F 0 "J1" H 1988 2355 50 0000 C CNN
-F 1 "RJ45Pads" H 1988 2446 50 0000 C CNN
-F 2 "flobs-KiCad-footprints:RJ45Pads_sloted" H 1850 2750 50 0001 C CNN
-F 3 "" H 1850 2750 50 0001 C CNN
- 1 1850 2900
+P 1100 1500
+F 0 "J1" H 1238 955 50 0000 C CNN
+F 1 "RJ45Pads" H 1238 1046 50 0000 C CNN
+F 2 "flobs-KiCad-footprints:RJ45Pads_sloted" H 1100 1350 50 0001 C CNN
+F 3 "" H 1100 1350 50 0001 C CNN
+ 1 1100 1500
-1 0 0 1
$EndComp
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-Wire Wire Line
- 4300 3000 4500 3000
-Wire Wire Line
- 4500 3000 4500 2150
-Wire Wire Line
- 4500 2150 2300 2150
-Wire Wire Line
- 2300 2150 2300 2950
-Wire Wire Line
- 2300 2950 1850 2950
-Wire Wire Line
- 3500 3000 2500 3000
-Wire Wire Line
- 2500 3000 2500 3050
-Wire Wire Line
- 2500 3050 1850 3050
+ 3000 1150 3000 1200
$Comp
L Device:C C1
U 1 1 5FF2388F
-P 5250 2900
-F 0 "C1" H 5365 2946 50 0000 L CNN
-F 1 "100nF" H 5365 2855 50 0000 L CNN
-F 2 "Capacitor_SMD:C_0402_1005Metric" H 5288 2750 50 0001 C CNN
-F 3 "~" H 5250 2900 50 0001 C CNN
-F 4 "C1525" H 5250 2900 50 0001 C CNN "JLCPCB#"
- 1 5250 2900
+P 4500 1500
+F 0 "C1" H 4615 1546 50 0000 L CNN
+F 1 "100nF" H 4615 1455 50 0000 L CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 4538 1350 50 0001 C CNN
+F 3 "~" H 4500 1500 50 0001 C CNN
+F 4 "C1525" H 4500 1500 50 0001 C CNN "JLCPCB#"
+ 1 4500 1500
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR01
U 1 1 5FF241D2
-P 1950 2450
-F 0 "#PWR01" H 1950 2300 50 0001 C CNN
-F 1 "VCC" H 1965 2623 50 0000 C CNN
-F 2 "" H 1950 2450 50 0001 C CNN
-F 3 "" H 1950 2450 50 0001 C CNN
- 1 1950 2450
+P 1200 1050
+F 0 "#PWR01" H 1200 900 50 0001 C CNN
+F 1 "VCC" H 1215 1223 50 0000 C CNN
+F 2 "" H 1200 1050 50 0001 C CNN
+F 3 "" H 1200 1050 50 0001 C CNN
+ 1 1200 1050
1 0 0 -1
$EndComp
Wire Wire Line
- 1950 2450 1950 2550
+ 1200 1050 1200 1150
Wire Wire Line
- 1950 2550 1850 2550
+ 1200 1150 1100 1150
$Comp
L power:VCC #PWR03
U 1 1 5FF254E7
-P 3900 2550
-F 0 "#PWR03" H 3900 2400 50 0001 C CNN
-F 1 "VCC" H 3915 2723 50 0000 C CNN
-F 2 "" H 3900 2550 50 0001 C CNN
-F 3 "" H 3900 2550 50 0001 C CNN
- 1 3900 2550
+P 3000 1150
+F 0 "#PWR03" H 3000 1000 50 0001 C CNN
+F 1 "VCC" H 3015 1323 50 0000 C CNN
+F 2 "" H 3000 1150 50 0001 C CNN
+F 3 "" H 3000 1150 50 0001 C CNN
+ 1 3000 1150
1 0 0 -1
$EndComp
$Comp
L power:VCC #PWR05
U 1 1 5FF26094
-P 5250 2650
-F 0 "#PWR05" H 5250 2500 50 0001 C CNN
-F 1 "VCC" H 5265 2823 50 0000 C CNN
-F 2 "" H 5250 2650 50 0001 C CNN
-F 3 "" H 5250 2650 50 0001 C CNN
- 1 5250 2650
+P 4500 1250
+F 0 "#PWR05" H 4500 1100 50 0001 C CNN
+F 1 "VCC" H 4515 1423 50 0000 C CNN
+F 2 "" H 4500 1250 50 0001 C CNN
+F 3 "" H 4500 1250 50 0001 C CNN
+ 1 4500 1250
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR04
U 1 1 5FF26603
-P 3900 3250
-F 0 "#PWR04" H 3900 3000 50 0001 C CNN
-F 1 "GND" H 3905 3077 50 0000 C CNN
-F 2 "" H 3900 3250 50 0001 C CNN
-F 3 "" H 3900 3250 50 0001 C CNN
- 1 3900 3250
+P 3000 1850
+F 0 "#PWR04" H 3000 1600 50 0001 C CNN
+F 1 "GND" H 3005 1677 50 0000 C CNN
+F 2 "" H 3000 1850 50 0001 C CNN
+F 3 "" H 3000 1850 50 0001 C CNN
+ 1 3000 1850
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR02
U 1 1 5FF26866
-P 1950 3350
-F 0 "#PWR02" H 1950 3100 50 0001 C CNN
-F 1 "GND" H 1955 3177 50 0000 C CNN
-F 2 "" H 1950 3350 50 0001 C CNN
-F 3 "" H 1950 3350 50 0001 C CNN
- 1 1950 3350
+P 1200 1950
+F 0 "#PWR02" H 1200 1700 50 0001 C CNN
+F 1 "GND" H 1205 1777 50 0000 C CNN
+F 2 "" H 1200 1950 50 0001 C CNN
+F 3 "" H 1200 1950 50 0001 C CNN
+ 1 1200 1950
1 0 0 -1
$EndComp
Wire Wire Line
- 1850 3250 1950 3250
+ 1100 1850 1200 1850
Wire Wire Line
- 1950 3250 1950 3350
+ 1200 1850 1200 1950
$Comp
L power:GND #PWR06
U 1 1 5FF27969
-P 5250 3150
-F 0 "#PWR06" H 5250 2900 50 0001 C CNN
-F 1 "GND" H 5255 2977 50 0000 C CNN
-F 2 "" H 5250 3150 50 0001 C CNN
-F 3 "" H 5250 3150 50 0001 C CNN
- 1 5250 3150
+P 4500 1750
+F 0 "#PWR06" H 4500 1500 50 0001 C CNN
+F 1 "GND" H 4505 1577 50 0000 C CNN
+F 2 "" H 4500 1750 50 0001 C CNN
+F 3 "" H 4500 1750 50 0001 C CNN
+ 1 4500 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4500 1250 4500 1350
+Wire Wire Line
+ 4500 1650 4500 1750
+Text Label 1200 1350 0 50 ~ 0
+SCK
+Text Label 1200 1450 0 50 ~ 0
+MOSI
+Text Label 1200 1550 0 50 ~ 0
+MISO
+Text Label 1200 1650 0 50 ~ 0
+~CS
+Text Label 3500 1400 0 50 ~ 0
+SCK
+Text Label 3500 1500 0 50 ~ 0
+MOSI
+Text Label 3500 1600 0 50 ~ 0
+MISO
+Text Label 2500 1600 2 50 ~ 0
+~CS
+Wire Wire Line
+ 1100 1350 1200 1350
+Wire Wire Line
+ 1100 1450 1200 1450
+Wire Wire Line
+ 1100 1550 1200 1550
+Wire Wire Line
+ 1100 1650 1200 1650
+Wire Wire Line
+ 2500 1600 2600 1600
+Wire Wire Line
+ 3400 1400 3500 1400
+Wire Wire Line
+ 3400 1500 3500 1500
+Wire Wire Line
+ 3400 1600 3500 1600
+$Comp
+L power:VCC #PWR0101
+U 1 1 60288DB8
+P 2350 1150
+F 0 "#PWR0101" H 2350 1000 50 0001 C CNN
+F 1 "VCC" H 2365 1323 50 0000 C CNN
+F 2 "" H 2350 1150 50 0001 C CNN
+F 3 "" H 2350 1150 50 0001 C CNN
+ 1 2350 1150
1 0 0 -1
$EndComp
Wire Wire Line
- 5250 2650 5250 2750
+ 2600 1400 2350 1400
+Wire Wire Line
+ 2350 1400 2350 1150
+Wire Wire Line
+ 2600 1500 2350 1500
Wire Wire Line
- 5250 3050 5250 3150
+ 2350 1500 2350 1400
+Connection ~ 2350 1400
+NoConn ~ 1100 1750
+NoConn ~ 1100 1250
$EndSCHEMATC